1. Field of the Invention
The present invention relates to a semiconductor element having a miniaturized structure, for example a transistor, particularly a field-effect type of transistor, typically a MOS (Metal Oxide Semiconductor) transistor (hereinafter, MOSFET) and a thin film transistor (TFT), and also relates to a method for manufacturing the same, and a method for manufacturing a semiconductor device comprising the semiconductor element having a miniaturized structure.
2. Description of the Related Art
In recent years, a demand for downsizing, lightweight, low-cost is increasing more and more in an electric appliance containing a semiconductor device (e.g., a video camera, a digital camera, a projector, a personal computer, a mobile computer, a mobile phone, and an electronic book). It is natural for users to demand for better performance if the electric appliance is downsized and lightened, and the better performance than that of current one is being demanded in the electric appliance. A function and the performance of the electric appliance depend on characteristics of LSI which constitutes a system and characteristics of a display device in a display portion of the electric appliance. Accordingly, research and development on miniaturization and high-integration concerning the semiconductor device such as LSI and on brightness and high-definition of a display device is being actively done. By improving the degree of the miniaturization and the integration, the more functions can be mounted on one chip, which permits the above-described demand for the downsizing, the lightweight and the high performance of the electric appliance to be satisfied. A high-definition image display can be realized by increasing the number of pixels in the display device.
For example, a system-on-chip is proposed, in which circuits such as an MPU, a memory, and an I/O interface constituting a system (function circuit) are mounted on one chip in monolithic and which can realize high speed, high reliability, and low electrical power consumption. Further, a system-on-panel that the above system (functional circuit) is formed by using TFTs and formed (mounted) on the same substrate as a display panel, is also proposed. Technology development of high-integration has been done in order to realize the purposes. It is necessary to manufacture a TFT having a high switching speed for the sake of manufacturing the above described system (function circuit) by using the TFTs. Accordingly, miniaturization of a TFT element as well as enhancing crystallinity of a semiconductor region of a TFT is required more and more, and an attempt to reduce a size of each part (a wiring width, a channel width, a diameter of a contact hole, and the like) of a semiconductor element is made.
It is not too much to say that a processing technique and an etching technique by alignment control and reduced projection exposure determine the miniaturization level for high-integration and miniaturization of the semiconductor device.
A manufacturing step of a semiconductor element, a TFT as a representative example, is shown in FIGS. 7A to 7C. A base film 702 is formed on a substrate 701, a semiconductor region 703 is formed thereon, and a gate insulating film 704 is formed thereover. Then, a conductive film is formed over the gate insulating film, and this conductive film is etched to form a gate electrode 705. After that, impurities are doped into the semiconductor region by using the gate electrode 705 as a mask, and activated to form a source region 703a, a drain region 703b, and a channel forming region 703c. An insulating film is formed thereover as an interlayer insulating film 706. Then, a resist (not shown) is applied, and the resist is exposed to light and developed to form resist masks 708a to 708c. Etching is performed by using the resist masks 708a to 708c as etching masks so as to form contact holes 707a and 707b to connect with the source region 703a and the drain region 703b of the semiconductor region.
A source electrode 709a and a drain electrode 709b are formed in the contact holes 707a and 707b to form a TFT as shown in FIG. 7B.
There is a problem that a gate electrode 715 and a source electrode 719a or a drain electrode 719b short-circuit, as shown in FIG. 7C, due to misalignment of a photomask when the resist masks 708a to 708c are formed, in a manufacturing step of a semiconductor element, particularly, a semiconductor element having a miniaturized structure. When the electrodes short-circuit, the semiconductor element can not operate normally, and thus, the yield of a semiconductor device having the semiconductor element decreases.
For the sake of avoiding this problem, when a contact hole is formed, it is necessary to precisely control alignment accuracy in a light-exposure step for forming a resist mask, accuracy of processing technique by reduced projection exposure, a finished dimension of a resist mask formed after developing of the resist, an etching amount of lateral direction when an interlayer insulating film is etched to form a contact hole, and the like, and therefore, this makes it extremely difficult to manufacture a semiconductor device.
When, as shown in FIG. 7B, when a semiconductor element, in particular, a TFT is designed, a margin “A” to assure a connection of the source region 703a and the drain region 703b, and the source electrode 709a and the drain electrode 709b is considered, and the size of the semiconductor region “B” is designed greater than a desired size (B-4A). Therefore, the area of the TFT increases, thereby inhibiting high-integration.